The present invention relates to a data processing system, and more particularly to a data processing system having a plurality of page sizes and capable of simultaneous address translation a plurality of logical addresses.
Examples of conventional data processing system of this kind are disclosed in the U.S. Pat. No. 4,691,281 and U.S. Pat. No. 5,058,003.
The former of the references cited above discloses a data processing system provided with an execution unit for generating a preselected logical address. The system includes a preselected logical page address and a logical internal address, and a preselected logical distance for indicating a real distance; first and second registers for storing the logical address and the logical distance, respectively; a request control circuit responsive to the logical distance supplied from the second register for generating an element number and number signals; an address generator responsive to the logical address, the logical distance and the number signals supplied from the first register, the second register and the request control circuit, respectively, for generating a plurality of local logical addresses; an address translation unit responsive to the logical address and logical distance supplied from the first register and the second register, respectively, for generating a plurality of real page addresses; an address combination circuit responsive to the plurality of real page addresses and the plurality of local logical addresses supplied from the address translation unit and the address generator, respectively, for generating a plurality of local real addresses equal in number to the plurality of local logical addresses; a memory access controller responsive to the plurality of local real addresses and the element number supplied from the address combination circuit and the request control circuit, respectively, for selecting the plurality of local real addresses, and sending them out simultaneously as specific addresses; and a memory for storing a plurality of data arrays or data sequences including consecutive data elements on the basis of the plurality of local real addresses supplied from the memory access controller. The data processing system performs simultaneous address translation of a plurality of pages.
The latter of the references discloses a data processing system including a directory-look-aside-table (DLAT) unit having a plurality of DLAT's, one provided for each of a plurality of page sizes, for performing address translation on the basis of either one of the DLAT's by supplying for each page size a congruence class selection bit in a virtual address composed of a segment number, a page number and a displacement value to the plurality of DLAT's.
These conventional data processing systems, however, have the following disadvantages.
First, since logical addresses of only one kind of page size are considered for an address space in the aforementioned data processing systems, address translation on a virtual computer system requiring a plurality of page sizes cannot be accomplished dynamically.
Second, since the aforementioned data processing systems manage memories for the same page size, if the data area is extremely great relative to the program area of the main storage, idle space will occur in this main storage, or the address translation table will take on a very large size, resulting in inefficient use of the main storage.
Third, since the aforementioned data processing systems limit the page size in a fixed manner, there is no freedom in memory management, inviting inflexibility in the operation of the data processing systems.